The present invention relates to a switching system for performing switching of time-division/ multiplex communication information such as voice and data by using fixed length cells each having a header for routing, and more particularly to a switching system suitable for integrated switching of line switched information, such as voice, and burst switched information such as data.
The advent of a flexible and economical switching system has been desired which can perform integrated handling of communications having various bit rates including a bit rate (64 Kb/s) of typical telephone quality voice as well as a low bit rate (several 100 b/s) of data and a high bit rate (several Mb/s) of video signal, and various properties (such as burst nature and real time nature).
A prospective method which might meet the above desire is one wherein fixed length cells each having a header containing information for routing are used and all pieces of information are subjected to uniform switching. Such a proposal has already been made by the present applicant as exemplified in a switching system disclosed in a literature entitled "A Study on an Integrated Switching Network", National Convention Record in commemoration of the 70th anniversary of the foundation of The Institute of Electronics, Information and Communication Engineers of Japan, 1987, switching division 1832. In this example, all pieces of communication information are transferred by using fixed length blocks called cells. In switching the cells, a header-driven space-division switch is foundamentally used wherein the time switching function is provided for individual incoming highways in order to avoid collision between a plurality of cells destined for the same destination within the space-division switch. Further, the time switching function is assisted by the provision of a memory for switching and a buffer memory for queuing in order that two modes can be handled of which one is a line switched mode for, for example, a telephone quality voice requiring real time nature and the other is a burst switched mode for transmitting data generated in burst fashion and permitted to be delayed to a certain extent. While a cell for the line switched mode is preferentially handled without being passed through the buffer memory to insure the real time nature, a cell for the burst switched mode undergoes queuing at the buffer memory and is processed when a time slot is idle.
As another example, "TDM Switching System" disclosed in JP-A-59-135994 may be referred to. In this example, the concept of handling communications having the two kinds of properties, the line switched mode and the burst switched mode, is not clearly described but this example has the function of switching fixed length cells on time basis by using a buffer memory. In this case, the same buffer memory is used for queuing and switching of the cells. For realization of queuing, cells are written in the buffer memory at write addresses which can be known from headers. Queuing means are provided for storing the cells in accordance with destinations.
When switching is effected using fixed length cells, due to the fact that destinations of the individual cells are not always distributed uniformly, it happens that cells destined for the same destination are concentrated at a time, resulting in a congestion condition or the memory overflows and cells are lost. In the first mentioned literature by the present applicant, buffer memories for queuing are provided in association with different destination outgoing highways for the sake of avoiding the congestion condition. Such buffer memories are required to store all of cells involved and to store so many cells that overflow does not occur, and besides they must be provided in association with the individual destinations. Accordingly, this construction faces a problem that many memories are needed. On the other hand, in the second mentioned switching system (JP-A-59-135994), a single buffer memory is provided for all the incoming highways and a plurality of queuing units for storage of addresses on the buffer memory are provided in association with individual destinations of cells. With this construction, the localization of destinations of cells can be absorbed by a relatively small number of memories. However, the write address for the buffer memory is used periodically, leading to a theoretically equivalent state that the buffer memory is fixedly divided to correspond to the individual destinations with the result that when queuing in a certain queue exceeds a predetermined amount, the same write address is again used in spite of the fact that cells which have not been read out yet remain, causing overwriting in the buffer memory. In this event, a cell subject to overwriting is erased accidentally.
To solve the above problems, Japanese patent application No. 63-102512 (corresponding to U.S. application Ser. No. 218217) proposes a switching system wherein a plurality of incoming highways are multiplexed to write cells in a single common main buffer, cells destined for outgoing highways are read out of the main buffer in the order of the outgoing highways and the read-out cells are demultiplexed and distributed to the plurality of outgoing highways. Used in buffering control of this main buffer are a FIFO (First-in First-out) buffer memory standing for an idle address buffer memory (hereinafter referred to as an idle address FIFO), a write register and a read register which are provided in association with the individual outgoing highways, and a next or succeeding address on the main buffer subjected to read/write at the same address as that for a cell concurrently with read/write of the cell. A cell stored in the main buffer and destined for a particular outgoing highway is subjected to buffering control of the type of a chain which starts at an address indicated by the read register, uses an address written next to the indicated address as a next or succeeding address, and ends at an address indicated by the write register. Thus, when a cell to be delivered to a particular outgoing highway is desired to be read out of the main buffer, the cell at an address indicated by a read register associated with the particular outgoing highway is read out of the main buffer together with a succeeding address, the cell is demultiplexed and delivered to the particular outgoing highway, and the succeeding address is written in the read register and that address which has been written in that read register to precede that succeeding address is sent as an empty or idle address to the idle address FIFO. On the other hand, when a cell to be delivered to a particular outgoing highway is desired to be written in the main buffer, the cell is written at an address indicated by a write register associated with the particular outgoing highway. At that time, an address generated from the idle address FIFO is written, as a succeeding address, in the main buffer at the same address as the indicated write address concurrently with writing of the cell and also in that write register. Through the above operation, a chain for each outgoing highway is updated.
With the switching system constructed as above, when a cell arriving at the system is written in the main buffer, an empty or idle address is generated from the single idle address FIFO regardless of an outgoing highway for which the cell is destined so that the cell can be written in the main buffer at any address as far as the main buffer is empty. If destinations of incoming cells are localized at a particular outgoing highway, the number of cells destined for other outgoing highways is decreased correspondingly and the capacity required of the main buffer remains unchanged.
Further, an address at which a cell is stored is not returned to the idle address FIFO before reading of the cell is completed and therefore, advantageously, overwriting of a new cell at the same address and consequent loss of an old cell stored thereat can be prevented.